公开(公告)号：US20230367553A1

公开(公告)日：2023-11-16

申请号：US18317666

申请日：2023-05-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hye-Ji KIM

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50

CPC classification number: G06F7/5443 ,  G06F7/50 ,  G06F7/523

Abstract: Disclosed herein are an apparatus and method for a multiplication operation based on an outer product. The apparatus may include first internal calculators, each of which generates an intermediate accumulation value by performing a Multiply-Accumulate (MAC) operation, second internal calculators, each of which generates a chunking accumulation value using the intermediate accumulation value, and accumulation data transmission paths for enabling the output of any one of the first internal calculators to be input to any one of the second internal calculators.

公开(公告)号：US20240062809A1

公开(公告)日：2024-02-22

申请号：US18499634

申请日：2023-11-01

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho HAN ,  Byung-Jo KIM ,  Ju-Yeob KIM ,  Hye-Ji KIM ,  Joo-Hyun LEE ,  Seong-Min KIM

IPC: G11C11/4096 ,  G06F7/544 ,  G06N3/063 ,  G11C11/4093 ,  G11C11/54

CPC classification number: G11C11/4096 ,  G06F7/5443 ,  G06N3/063 ,  G11C11/4093 ,  G11C11/54

Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.

公开(公告)号：US20240362297A1

公开(公告)日：2024-10-31

申请号：US18502330

申请日：2023-11-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hye-Ji KIM

IPC: G06F17/16 ,  G06F7/544

CPC classification number: G06F17/16 ,  G06F7/5443

Abstract: Disclosed herein are an outer product-based matrix-vector multiplication operation apparatus and a method using the same. The outer product-based matrix-vector multiplication operation apparatus includes internal calculators, each configured to generate an accumulated value by performing a Multiply-Accumulation (MAC) operation, an internal data transmission path configured to simultaneously provide a vector element to two or more internal calculators, and at least one multiplexer configured to select any one of the vector element and a vector of a matrix, wherein a first input port of each of the internal calculators is connected to one of vectors of the matrix and a second input port of each of the internal calculators is connected to the vector element.

公开(公告)号：US20230259581A1

公开(公告)日：2023-08-17

申请号：US18109690

申请日：2023-02-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Won JEON ,  Young-Su KWON ,  Ju-Yeob KIM ,  Hyun-Mi KIM ,  Hye-Ji KIM ,  Chun-Gi LYUH ,  Mi-Young LEE ,  Jae-Hoon CHUNG ,  Yong-Cheol CHO ,  Jin-Ho HAN

IPC: G06F17/16 ,  G06F5/01

CPC classification number: G06F17/16 ,  G06F5/012

Abstract: Disclosed herein is a method for outer-product-based matrix multiplication for a floating-point data type includes receiving first floating-point data and second floating-point data and performing matrix multiplication on the first floating-point data and the second floating-point data, and the result value of the matrix multiplication is calculated based on the suboperation result values of floating-point units.