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公开(公告)号:US11604755B2
公开(公告)日:2023-03-14
申请号:US17196124
申请日:2021-03-09
Applicant: Cisco Technology, Inc.
Inventor: Jayaprakash Balachandran , Bidyut Kanti Sen , Kenny Lieu , Dattatri N. Mattur
Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.
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公开(公告)号:US11004476B2
公开(公告)日:2021-05-11
申请号:US16398861
申请日:2019-04-30
Applicant: Cisco Technology, Inc.
Inventor: Hoi San Leung , Steve Zhijian Chen , Richard Jiang Li , Minh-Thanh T. Vo , Shameem Ahmed , Kenny Lieu
IPC: G11C5/04 , G11C5/06 , H05K1/18 , G06F30/392 , G06F30/394
Abstract: In one embodiment, a printed circuit board (PCB) has a first central processing unit (CPU) socket and a second CPU socket substantially in line with the first CPU socket, and also has a first plurality of dual in-line memory module (DIMM) sockets interconnected with the first CPU socket and a second plurality of DIMM sockets interconnected with the second CPU socket (in a direction parallel to the first plurality of DIMM sockets). The first plurality of DIMM sockets are arranged on the PCB in at least a first column and a second column of DIMM sockets, and the second plurality of DIMM sockets are arranged on the PCB in at least the second column and a third column of DIMM sockets, such that the second column of DIMM sockets contains interleaved DIMM sockets from each of the first plurality of DIMM sockets and the second plurality of DIMM sockets.
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公开(公告)号:US20220292041A1
公开(公告)日:2022-09-15
申请号:US17196124
申请日:2021-03-09
Applicant: Cisco Technology, Inc.
Inventor: Jayaprakash Balachandran , Bidyut Kanti Sen , Kenny Lieu , Dattatri N. Mattur
Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.
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公开(公告)号:US20200349983A1
公开(公告)日:2020-11-05
申请号:US16398861
申请日:2019-04-30
Applicant: Cisco Technology, Inc.
Inventor: Hoi San Leung , Steve Zhijian Chen , Richard Jiang Li , Minh-Thanh T. Vo , Shameem Ahmed , Kenny Lieu
Abstract: In one embodiment, a printed circuit board (PCB) has a first central processing unit (CPU) socket and a second CPU socket substantially in line with the first CPU socket, and also has a first plurality of dual in-line memory module (DIMM) sockets interconnected with the first CPU socket and a second plurality of DIMM sockets interconnected with the second CPU socket (in a direction parallel to the first plurality of DIMM sockets). The first plurality of DIMM sockets are arranged on the PCB in at least a first column and a second column of DIMM sockets, and the second plurality of DIMM sockets are arranged on the PCB in at least the second column and a third column of DIMM sockets, such that the second column of DIMM sockets contains interleaved DIMM sockets from each of the first plurality of DIMM sockets and the second plurality of DIMM sockets.
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