公开(公告)号：US11604755B2

公开(公告)日：2023-03-14

申请号：US17196124

申请日：2021-03-09

Applicant: Cisco Technology, Inc.

Inventor： Jayaprakash Balachandran ,  Bidyut Kanti Sen ,  Kenny Lieu ,  Dattatri N. Mattur

IPC: G06F13/40 ,  G06F3/12 ,  H05K7/10

Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

公开(公告)号：US20220292041A1

公开(公告)日：2022-09-15

申请号：US17196124

申请日：2021-03-09

Applicant: Cisco Technology, Inc.

Inventor： Jayaprakash Balachandran ,  Bidyut Kanti Sen ,  Kenny Lieu ,  Dattatri N. Mattur

IPC: G06F13/40 ,  H05K7/10

Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.