公开(公告)号：US10917009B2

公开(公告)日：2021-02-09

申请号：US15672652

申请日：2017-08-09

申请人： California Institute of Technology

发明人： Philippe C. Adell ,  Ming Sun ,  Bertan Bakkaloglu

IPC分类号： H02M3/157 ,  H02M3/158 ,  H03L7/085 ,  H03L7/093 ,  H02M3/156 ,  H04B7/14

摘要： An autozeroed comparator controls a frequency fsw of the input voltage inputted to a DC/DC converter. A digital frequency synchronization circuit is connected to the autozeroed comparator so as to form a phase locked loop, wherein the DES circuit controls the hysteretic window of the autozeroed comparator so as to lock fsw to a clock reference frequency. A plurality of slave phase circuits may be connected to the master phase circuit including the DFS circuit and the autozeroed comparator. Duty cycle calibration circuits adjust a duty cycle signal applied to each of the slave phase circuits, in response to average current measured in the slave phase circuits, so that each slave phase circuit is synchronized with the master phase circuit. A 6 A 90.5% peak efficiency 4-phase hysteretic quasi-current-mode buck converter is provided with constant frequency and maximum ±1.5% current mismatch between the slave phases and the master phase.

公开(公告)号：US20180048232A1

公开(公告)日：2018-02-15

申请号：US15672652

申请日：2017-08-09

申请人： California Institute of Technology

发明人： Philippe C. Adell ,  Ming Sun ,  Bertan Bakkaloglu

IPC分类号： H02M3/157 ,  H02M3/158

CPC分类号： H02M3/157 ,  H02M3/1563 ,  H02M3/158 ,  H02M3/1584 ,  H03L7/085 ,  H03L7/093 ,  H04B7/14

摘要： An autozeroed comparator controls a frequency fsw of the input voltage inputted to a DC/DC converter. A digital frequency synchronization circuit is connected to the autozeroed comparator so as to form a phase locked loop, wherein the DES circuit controls the hysteretic window of the autozeroed comparator so as to lock fsw to a clock reference frequency. A plurality of slave phase circuits may be connected to the master phase circuit including the DFS circuit and the autozeroed comparator. Duty cycle calibration circuits adjust a duty cycle signal applied to each of the slave phase circuits, in response to average current measured in the slave phase circuits, so that each slave phase circuit is synchronized with the master phase circuit. A 6 A 90.5% peak efficiency 4-phase hysteretic quasi-current-mode buck converter is provided with constant frequency and maximum ±1.5% current mismatch between the slave phases and the master phase.