公开(公告)号：US20210034257A1

公开(公告)日：2021-02-04

申请号：US16853617

申请日：2020-04-20

Applicant: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.

Inventor： Yingnan XU ,  Xueliang DU

IPC: G06F3/06

Abstract: Embodiments of the present disclosure relate to a data access method and apparatus, an electronic device, and a computer-readable storage medium. The method may include, in response to receiving a first access request sent from a first access device in a set of access devices to a first storage device in a set of storage devices, sending an updated first access request to the first storage device, the first access request including identity information of the first access device. The method may further include, in response to receiving data from the set of storage devices, determining identity information included in the data. The method may further include, in response to the determined identity information being corresponding to the identity information of the first access device, sending the data to the first access device.

公开(公告)号：US20210318883A1

公开(公告)日：2021-10-14

申请号：US17343139

申请日：2021-06-09

Applicant: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.

Inventor： Yingnan XU ,  Xueliang DU

IPC: G06F9/38 ,  G06F9/30

Abstract: The invention discloses an apparatus and method for writing back an instruction execution result. The apparatus for writing back the instruction execution result includes: a first writing port, coupled between a first execution unit with a first execution delay and a register file, and configured to receive a first execution result from the first execution unit, and to write the first execution result back to a first register unit in the register file based on a first writing address; and a second writing port, coupled between a second execution unit with a second execution delay different from the first execution delay and the register file, and configured to receive a second execution result from the second execution unit, and to write the second execution result back to a second register unit in the register file based on a second writing address.

公开(公告)号：US20210406032A1

公开(公告)日：2021-12-30

申请号：US17149476

申请日：2021-01-14

Applicant: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.

Inventor： Baofu ZHAO ,  Xueliang DU ,  Kang AN ,  Yingnan XU ,  Chao TANG

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345

Abstract: The present application discloses a complex computing device, a complex computing method, an artificial intelligence chip and an electronic apparatus, and relates to a field of artificial intelligence chips. One of the solutions includes: an input interface receives complex computing instructions and arbitrates each complex computing instruction to a corresponding computing component respectively, according to the computing types in the respective complex computing instructions; each computing component is connected to the input interface, acquires a source operand from a complex computing instruction to perform complex computing, and generates computing result instruction to feed back to an output interface; the output interface arbitrates the computing result in each computing result instruction to the corresponding instruction source respectively, according to the instruction source identifier in each computing result instruction.

公开(公告)号：US20210173653A1

公开(公告)日：2021-06-10

申请号：US17036596

申请日：2020-09-29

Applicant: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.

Inventor： Chao TANG ,  Xueliang DU ,  Yingnan XU

IPC: G06F9/38 ,  G06F9/30

Abstract: The present disclosure discloses an instruction prefetching method, a device and a medium. The present disclosure relates to a data storage technology, the method includes the following. Instructions in a target buffer are precompiled before a processor core fetches a required instruction from the target buffer corresponding to the processor core; if it is determined that a jump instruction exists in the target buffer and a branch instruction corresponding to the jump instruction is not cached in the target buffer according to a precompiled result, the branch instruction is prefetched from an icache into a candidate buffer corresponding to the processor core to wait for the processor core to fetch the branch instruction from the candidate buffer; the target buffer and the candidate buffer are alternately reused during instruction prefetching.