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公开(公告)号：US20210406032A1
公开(公告)日：2021-12-30
申请号：US17149476
申请日：2021-01-14
Inventor： Baofu ZHAO , Xueliang DU , Kang AN , Yingnan XU , Chao TANG
Abstract: The present application discloses a complex computing device, a complex computing method, an artificial intelligence chip and an electronic apparatus, and relates to a field of artificial intelligence chips. One of the solutions includes: an input interface receives complex computing instructions and arbitrates each complex computing instruction to a corresponding computing component respectively, according to the computing types in the respective complex computing instructions; each computing component is connected to the input interface, acquires a source operand from a complex computing instruction to perform complex computing, and generates computing result instruction to feed back to an output interface; the output interface arbitrates the computing result in each computing result instruction to the corresponding instruction source respectively, according to the instruction source identifier in each computing result instruction.
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公开(公告)号：US20210342149A1
公开(公告)日：2021-11-04
申请号：US17377548
申请日：2021-07-16
Inventor： Chao TANG , Xueliang DU
IPC: G06F9/30
Abstract: The disclosure discloses a method for executing instructions, a device and a computer readable storage medium. The detailed implementation includes: obtaining a first memory access instruction for execution, in which the first memory access instruction includes a first address range of a memory to be accessed; in response to detecting a predetermined instruction for monitoring an accessed address range of the memory, executing the predetermined instruction to obtain a remaining address range not accessed by the first memory access instruction in the first address range; comparing the remaining address range with a second address range included in a second memory access instruction to be executed; and suspending execution of the second memory access instruction in response to the remaining address range at least partially overlapping with the second address range.
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公开(公告)号：US20210173653A1
公开(公告)日：2021-06-10
申请号：US17036596
申请日：2020-09-29
Inventor： Chao TANG , Xueliang DU , Yingnan XU
Abstract: The present disclosure discloses an instruction prefetching method, a device and a medium. The present disclosure relates to a data storage technology, the method includes the following. Instructions in a target buffer are precompiled before a processor core fetches a required instruction from the target buffer corresponding to the processor core; if it is determined that a jump instruction exists in the target buffer and a branch instruction corresponding to the jump instruction is not cached in the target buffer according to a precompiled result, the branch instruction is prefetched from an icache into a candidate buffer corresponding to the processor core to wait for the processor core to fetch the branch instruction from the candidate buffer; the target buffer and the candidate buffer are alternately reused during instruction prefetching.
