公开(公告)号：US20180323042A1

公开(公告)日：2018-11-08

申请号：US15957054

申请日：2018-04-19

Applicant: Applied Materials, Inc.

Inventor： Haitao WANG ,  Anwar HUSAIN ,  Kartik RAMASWAMY ,  Jason A. KENNEY ,  Jeffrey LUDWIG ,  Chunlei ZHANG ,  Wonseok LEE

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/67069 ,  H01L21/6833

Abstract: The present disclosure generally relates to methods of and apparatuses for controlling a plasma sheath near a substrate edge. The apparatus includes an auxiliary electrode that may be positioned adjacent an electrostatic chuck. The auxiliary electrode is recursively fed from a power source using equal length and equal impedance feeds. The auxiliary electrode is vertically actuatable, and is tunable with respect to ground or other frequencies responsible for plasma generation. Methods of using the same are also provided.

公开(公告)号：US20240162007A1

公开(公告)日：2024-05-16

申请号：US17984772

申请日：2022-11-10

Applicant: Applied Materials, Inc.

Inventor： Deyang LI ,  Sunil SRINIVASAN ,  Yi-Chuan CHOU ,  Shahid RAUF ,  Kuan-Ting LIU ,  Jason A. KENNEY ,  Chung LIU ,  Olivier P. JOUBERT ,  Shreeram Jyoti DASH ,  Aaron EPPLER ,  Michael Thomas NICHOLS

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32128 ,  H01J37/32146 ,  H01J2237/3341 ,  H01J2237/3346

Abstract: Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing. The ability to synchronize and control waveform characteristics of a voltage waveform bias established on a substrate during processing allows for an improved control of the generated plasma and process of forming, for example, high-aspect ratio features in the surface of the substrate by a reactive ion etching process. As a result, greater precision for plasma processing can be achieved, which is described herein in more detail.

公开(公告)号：US20200185256A1

公开(公告)日：2020-06-11

申请号：US16657604

申请日：2019-10-18

Applicant: Applied Materials, Inc.

Inventor： Andrew NGUYEN ,  Xue CHANG ,  Shahid RAUF ,  Jason A. KENNEY

IPC: H01L21/687 ,  H01L21/683

Abstract: Implementations of the present disclosure provide a process kit for an electrostatic chuck. In one implementation, a substrate support assembly is provided. The substrate support assembly includes an electrostatic chuck having a first recess formed in an upper portion of the electrostatic chuck. A process kit surrounds the electrostatic chuck. The process kit includes an inner ring and an outer ring disposed radially outward of the inner ring. The outer ring includes a second recess formed in an upper portion of the upper ring. The inner ring is positioned within and is supported by the first recess and the second recess. An upper surface of the inner ring and an upper surface of the outer ring are co-planar.

公开(公告)号：US20170256435A1

公开(公告)日：2017-09-07

申请号：US15436936

申请日：2017-02-20

Applicant: Applied Materials, Inc.

Inventor： Olivier JOUBERT ,  Jason A. KENNEY ,  Sunil SRINIVASAN ,  James ROGERS ,  Rajinder DHINDSA ,  Vedapuram S. ACHUTHARAMAN ,  Olivier LUERE

IPC: H01L21/687 ,  H01J37/32 ,  H01L21/683

CPC classification number: H01L21/68735 ,  H01J37/32082 ,  H01J37/32623 ,  H01J37/32642 ,  H01J37/32715 ,  H01J2237/3321 ,  H01J2237/334 ,  H01L21/6833

Abstract: The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 μm, and a height difference between the substrate and the edge ring is less than about (+/−) 300 μm. The resistivity of the ring is less than about 50 Ohm-cm.