公开(公告)号：US09336003B2

公开(公告)日：2016-05-10

申请号：US13749999

申请日：2013-01-25

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  Shyam Sundar Balasubramanian ,  Conrado Blasco-Allue

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/4881 ,  G06F9/4887

Abstract: In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

Abstract translation: 在一个实施例中，处理器包括被配置为提供由多个并行执行管线执行的操作的多级调度电路。 多级调度电路可以包括多个调度缓冲器，每个调度缓冲器耦合到多个保留站。 每个保留站可以耦合到相应的执行流水线，并且可以被配置为调度用于在相应的执行流水线中执行的指令操作（op）。 耦合到每个调度缓冲器的保留站组可以是不重叠的。 因此，如果在给定的执行流水线中执行给定的操作，则操作可以被发送到调度缓冲器，该调度缓冲器耦合到向给定的执行流水线提供操作的保留站。

公开(公告)号：US09824171B2

公开(公告)日：2017-11-21

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

公开(公告)号：US20170039299A1

公开(公告)日：2017-02-09

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract translation: 在一些实施例中，寄存器文件电路设计过程包括指示自动集成电路设计程序产生寄存器文件电路设计，包括提供单元电路设计并指示自动化集成电路设计程序产生选择设计，预解码 设计和数据门控设计。 单元电路设计描述了具有特定布置的多个选择电路。 选择设计描述了包括具有特定布置的相应多个选择电路的多个复制电路。 预解码设计描述了预解码电路，其被配置为识别由写指令的一部分识别的多个条目。 数据门控设计描述了数据选通电路，其响应于未识别相应条目的预解码电路而配置，以禁止连接到各个条目的相应写入选择电路的数据输入。

公开(公告)号：US20140215188A1

公开(公告)日：2014-07-31

申请号：US13749999

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  Shyam Sundar Balasubramanian ,  Conrado Blasco-Allue

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/4881 ,  G06F9/4887

Abstract: In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

Abstract translation: 在一个实施例中，处理器包括被配置为提供由多个并行执行管线执行的操作的多级调度电路。 多级调度电路可以包括多个调度缓冲器，每个调度缓冲器耦合到多个保留站。 每个保留站可以耦合到相应的执行流水线，并且可以被配置为调度用于在相应的执行流水线中执行的指令操作（op）。 耦合到每个调度缓冲器的保留站组可以是不重叠的。 因此，如果在给定的执行流水线中执行给定的操作，则操作可以被发送到调度缓冲器，该调度缓冲器耦合到向给定的执行流水线提供操作的保留站。