公开(公告)号：US09317102B2

公开(公告)日：2016-04-19

申请号：US13733775

申请日：2013-01-03

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。

公开(公告)号：US20140189411A1

公开(公告)日：2014-07-03

申请号：US13733775

申请日：2013-01-03

Applicant: APPLE INC.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。