公开(公告)号：US20240385842A1

公开(公告)日：2024-11-21

申请号：US18774678

申请日：2024-07-16

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US12175248B2

公开(公告)日：2024-12-24

申请号：US18305151

申请日：2023-04-21

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Deepankar Duggal ,  Debasish Chandra ,  Niket K Choudhary ,  Richard F. Russo

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a control transfer instruction is mispredicted, a load instruction may have been executed on the wrong path. In disclosed embodiments, result storage circuitry records information that indicates destination registers of speculatively-executed load instructions including a first load instruction. Control flow tracker circuitry may store information indicating a reconvergence point for the control transfer instruction. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine that the first load instruction does not depend on data from any instruction between the control transfer instruction and the reconvergence point, and use, as a result of the first load instruction, a value from a recorded destination register that was written based on speculative execution of the first load, notwithstanding the misprediction of the control transfer instruction.

公开(公告)号：US12229561B1

公开(公告)日：2025-02-18

申请号：US17933037

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Madhu Sudan Hari ,  Mridul Agarwal ,  Kulin N Kothari ,  John D Pape ,  Niket K Choudhary

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F12/1027

Abstract: A system may include multiple processors. One of the processors may receive an indication of a data synchronization barrier (DSB) instruction in another processor that follows a translation look-ahead buffer invalidate (TLBI) instruction to invalidate an entry of a translation look-ahead buffer. The processor may determine whether instructions are pending in the processor for which the virtual addresses used for memory accesses have been translated to physical addresses before receiving the DSB indication. If there are such pending instructions, the processor may provide, after these instructions retire, an indication to the other processor as a response to the DSB indication.

公开(公告)号：US20230244494A1

公开(公告)日：2023-08-03

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/30196 ,  G06F9/30058

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US12067399B2

公开(公告)日：2024-08-20

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3806 ,  G06F9/3844

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US11809874B2

公开(公告)日：2023-11-07

申请号：US17590722

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia ,  Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30058 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885

Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.