公开(公告)号：US20240329933A1

公开(公告)日：2024-10-03

申请号：US18127650

申请日：2023-03-28

Applicant: Apple Inc.

Inventor： Lei Wang ,  Jaewon Shin ,  Seungjin Lee ,  Ji Liang Song ,  Michael L. Liu ,  Christopher L. Mills

IPC: G06F7/544 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06N3/063

Abstract: Embodiments of the present disclosure relate to a multiply-accumulator circuit that includes a main multiplier circuit operable in a floating-point mode or an integer mode and a supplemental multiplier circuit that operates in the integer mode. The main multiplier circuit generates a multiplied output that undergoes subsequent operations including a shifting operation in the floating-point mode whereas the supplemental multiplier generates another multiplied output that does not undergo any shifting operations. Hence, in the integer mode, two parallel multiply-add operations may be performed by the two multiplier circuits, and therefore accelerate the multiply-adder operations. Due to the lack of additional shifters associated with the supplemental multiplier circuit, the multiply-accumulator circuit does not have a significantly increased footprint.

公开(公告)号：US20240053962A1

公开(公告)日：2024-02-15

申请号：US17885364

申请日：2022-08-10

Applicant: Apple Inc.

Inventor： Michael L. Liu ,  Yash H. Malviya

IPC: G06F7/50 ,  G06F7/02

CPC classification number: G06F7/50 ,  G06F7/02

Abstract: An integrated circuit can include absolute difference circuitry configured to compute an absolute difference value. The absolute difference circuitry may include a comparison logic, a single adder, and a multiplexer. The comparison logic may receive a first input value and a second input value and may generate a comparison value based on whether the first input value exceeds the second input value. The adder may compute a sum of the first input value, an inverted version of the second input value, and the comparison value. The multiplexer may receive the sum and an inverted version of the sum and may output either the sum or the inverted version of the sum based on the comparison value to produce the absolute difference value.

公开(公告)号：US20150235634A1

公开(公告)日：2015-08-20

申请号：US14183321

申请日：2014-02-18

Applicant: Apple Inc.

Inventor： Michael L. Liu ,  Liang Deng

IPC: G09G5/395 ,  H03K19/173 ,  H03K19/00

CPC classification number: G09G5/395 ,  G06F7/533 ,  H03K19/0013 ,  H03K19/1737

Abstract: Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.

Abstract translation: 公开了涉及不对称电路的技术。 在一些实施例中，存储元件被配置为在时间间隔期间将第一输入值保持为非对称电路的输入。 例如，在一个实施例中，时间间隔可以对应于视频数据的帧，并且存储元件可以被配置为存储用于视频数据帧的滤波器系数。 在一些实施例中，存储元件可以被配置为将该值存储为用于由非对称电路进行的多个操作的常数。 在一些实施例中，非对称电路被配置为基于第一输入值和一组第二输入值中的相应值来产生多个输出值。 在一些实施例中，非对称电路是泄漏功率不对称和/或关键路径不对称。 这可能会提高性能和/或降低功耗。

公开(公告)号：US20240329929A1

公开(公告)日：2024-10-03

申请号：US18127528

申请日：2023-03-28

Applicant: Apple Inc.

Inventor： Lei Wang ,  Kenneth W. Waters ,  Michael L. Liu ,  Ji Liang Song ,  Youchang Kim

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50

Abstract: Embodiments relate to performing multiply-accumulator operation on asymmetrically quantized input data and kernel data in a neural processor. Instead of adjusting to the input data at a multiply-accumulator to account for the asymmetric quantization of the input data, an adjusted bias for the multiply-accumulator operation is computed beforehand and stored in the multiply-accumulator. On the other hand, kernel coefficients derived from the kernel data are adjusted at the multiply-accumulator to account for the asymmetric quantization. In this way, computational complexity associated with asymmetric quantization may be reduced while increasing the efficiency of the convolution operations at the neural processor.

公开(公告)号：US09607586B2

公开(公告)日：2017-03-28

申请号：US14183321

申请日：2014-02-18

Applicant: Apple Inc.

Inventor： Michael L. Liu ,  Liang Deng

IPC: G09G5/395 ,  H03K19/00 ,  G06F7/533 ,  H03K19/173

CPC classification number: G09G5/395 ,  G06F7/533 ,  H03K19/0013 ,  H03K19/1737

Abstract: Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.