公开(公告)号：US11093249B2

公开(公告)日：2021-08-17

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206 ,  G06F12/0875

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US20190196834A1

公开(公告)日：2019-06-27

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30058 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US10223123B1

公开(公告)日：2019-03-05

申请号：US15133804

申请日：2016-04-20

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F1/3287 ,  G06F1/3234

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.