公开(公告)号：US20250110740A1

公开(公告)日：2025-04-03

申请号：US18798800

申请日：2024-08-08

Applicant: Apple Inc.

Inventor： Evan R. Lissoos ,  Anurag Choudhury ,  Casper R. van Benthem

IPC: G06F9/30

Abstract: Techniques are disclosed involving selective toggle suppression in multiplexed datapaths. An embodiment of an apparatus includes a storage circuit and a control circuit. The storage circuit is configured to store a set of previous select values transmitted as a set of previous select signals to a multiplexer within a datapath of a computing device. The control circuit is configured to determine, based at least in part on the set of previous select signals and a set of input toggle likelihood signals, whether to maintain the set of previous select signals or provide a set of updated select signals to the multiplexer. In a further embodiment, the control circuit is further configured to determine whether a value of a particular input toggle likelihood signal corresponding to a previously selected data input of the multiplexer indicates a designation of the previously-selected data input as likely to receive a data value change.

公开(公告)号：US20240404172A1

公开(公告)日：2024-12-05

申请号：US18329055

申请日：2023-06-05

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Casper R. van Benthem

IPC: G06T15/06 ,  G06T15/00

Abstract: Techniques are disclosed relating to ray intersection tests for ray tracing in graphics processors. In some embodiments, a ray cache stores, transformed ray direction corresponding to a transform of a ray based on its dominant direction axis. Ray intersect acceleration circuitry may determine whether a ray intersects a bounding volume of a bounding volume hierarchy (BVH) data structure. Ray-plane test circuitry may perform a set of six ray-plane tests for the bounding volume using at most four floating-point multiplication operations by four multiplier circuits. The floating-point operations may operate on the transformed ray direction components from the ray cache circuitry and coordinate information for the bounding volume. Disclosed techniques may reduce area and power consumption by avoiding multiplier circuitry for some ray-plane tests.