公开(公告)号：US20130087823A1

公开(公告)日：2013-04-11

申请号：US13806703

申请日：2011-08-03

Applicant: Yao-Jun Tsai ,  Chen-Peng Hsu ,  Kuo-Feng Lin ,  Hsun-Chin Liu ,  Ji-Feng Chen ,  Hung-Lieh Hu ,  Chien-Jen Sun

Inventor： Yao-Jun Tsai ,  Chen-Peng Hsu ,  Kuo-Feng Lin ,  Hsun-Chin Liu ,  Ji-Feng Chen ,  Hung-Lieh Hu ,  Chien-Jen Sun

IPC: H01L33/20 ,  H01L33/10

CPC classification number: H01L33/62 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/10 ,  H01L33/20 ,  H01L33/38 ,  H01L33/48 ,  H01L2224/06102 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/24 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/8592 ,  H01L2224/92244 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.

Abstract translation: 提供一种发光二极管芯片，发光二极管封装结构及其形成方法。 发光二极管芯片包括具有多个空隙的接合层，或者发光二极管芯片的周围边界与接合层之间的最小水平距离大于0.发光二极管芯片，发光 二极管封装结构和方法可以提高产品产量并提高发光效率。

公开(公告)号：US20120034714A1

公开(公告)日：2012-02-09

申请号：US13197677

申请日：2011-08-03

Applicant: Yao-Jun TSAI ,  Chen-Peng HSU ,  Kuo-Feng LIN ,  Hsun-Chih LIU ,  Hung-Lieh HU ,  Chien-Jen SUN

Inventor： Yao-Jun TSAI ,  Chen-Peng HSU ,  Kuo-Feng LIN ,  Hsun-Chih LIU ,  Hung-Lieh HU ,  Chien-Jen SUN

IPC: H01L21/66 ,  H01L33/36

CPC classification number: H01L33/0095 ,  H01L33/20 ,  H01L33/44 ,  H01L2933/0016

Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.

Abstract translation: 提供了一种制造晶片级发光二极管结构的方法。 该方法包括：提供衬底，其中第一半导体层，发光层和第二半导体层依次设置在衬底上; 通过图案化工艺对第一半导体层，发光层和第二半导体层进行处理，以形成设置在第二凹部上的第一凹部，第二凹部，层叠结构，以及设置在第二凹部 凹陷部分，其中所述堆叠结构包括图案化的第二半导体层，图案化发光层和图案化的第一半导体层; 在第一凹部的残留的第一半导体层上形成第一电极; 以及形成相应地设置在所述第二凹陷部分的图案化的第二半导体层上的第二电极。

公开(公告)号：US08759865B2

公开(公告)日：2014-06-24

申请号：US13806703

申请日：2011-08-03

Applicant: Yao-Jun Tsai ,  Chen-Peng Hsu ,  Kuo-Feng Lin ,  Hsun-Chih Liu ,  Ji-Feng Chen ,  Hung-Lieh Hu ,  Chien-Jen Sun

Inventor： Yao-Jun Tsai ,  Chen-Peng Hsu ,  Kuo-Feng Lin ,  Hsun-Chih Liu ,  Ji-Feng Chen ,  Hung-Lieh Hu ,  Chien-Jen Sun

IPC: H01L33/20 ,  H01L33/38 ,  H01L33/48 ,  H01L33/10 ,  H01L33/62 ,  H01L33/00

CPC classification number: H01L33/62 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/10 ,  H01L33/20 ,  H01L33/38 ,  H01L33/48 ,  H01L2224/06102 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/24 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/8592 ,  H01L2224/92244 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.

Abstract translation: 提供一种发光二极管芯片，发光二极管封装结构及其形成方法。 发光二极管芯片包括具有多个空隙的接合层，或者发光二极管芯片的周围边界与接合层之间的最小水平距离大于0.发光二极管芯片，发光 二极管封装结构和方法可以提高产品产量并提高发光效率。

公开(公告)号：US09178107B2

公开(公告)日：2015-11-03

申请号：US13197677

申请日：2011-08-03

Applicant: Yao-Jun Tsai ,  Chen-Peng Hsu ,  Kuo-Feng Lin ,  Hsun-Chih Liu ,  Hung-Lieh Hu ,  Chien-Jen Sun

Inventor： Yao-Jun Tsai ,  Chen-Peng Hsu ,  Kuo-Feng Lin ,  Hsun-Chih Liu ,  Hung-Lieh Hu ,  Chien-Jen Sun

IPC: H01L33/00 ,  H01L33/20 ,  H01L33/44

CPC classification number: H01L33/0095 ,  H01L33/20 ,  H01L33/44 ,  H01L2933/0016

Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.

Abstract translation: 提供了一种制造晶片级发光二极管结构的方法。 该方法包括：提供衬底，其中第一半导体层，发光层和第二半导体层依次设置在衬底上; 通过图案化工艺对第一半导体层，发光层和第二半导体层进行处理，以形成设置在第二凹部上的第一凹部，第二凹部，层叠结构，以及设置在第二凹部 凹陷部分，其中所述堆叠结构包括图案化的第二半导体层，图案化发光层和图案化的第一半导体层; 在第一凹部的残留的第一半导体层上形成第一电极; 以及形成相应地设置在所述第二凹陷部分的图案化的第二半导体层上的第二电极。