公开(公告)号：US20080103753A1

公开(公告)日：2008-05-01

申请号：US11929450

申请日：2007-10-30

申请人： Suresh Rajan ,  Keith Schakel ,  Michael Sebastian Smith ,  David Wang ,  Frederick Weber

发明人： Suresh Rajan ,  Keith Schakel ,  Michael Sebastian Smith ,  David Wang ,  Frederick Weber

IPC分类号： G06F9/455

CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

公开(公告)号：US20070192563A1

公开(公告)日：2007-08-16

申请号：US11672924

申请日：2007-02-08

申请人： Suresh Rajan ,  Keith Schakel ,  Michael Smith ,  David Wang ,  Frederick Weber

发明人： Suresh Rajan ,  Keith Schakel ,  Michael Smith ,  David Wang ,  Frederick Weber

IPC分类号： G06F12/00

CPC分类号： G06F12/0292 ,  G06F13/28 ,  G06F13/4243 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4093 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

摘要翻译： 提供了一种存储器电路系统和方法。 接口电路能够与多个存储器电路和系统通信。 在使用中，接口电路可操作地转换与在系统和存储器电路之间传送的命令相关联的地址。

公开(公告)号：US20080104314A1

公开(公告)日：2008-05-01

申请号：US11929483

申请日：2007-10-30

申请人： Suresh Rajan ,  Keith Schakel ,  Michael Smith ,  David Wang ,  Frederick Weber

发明人： Suresh Rajan ,  Keith Schakel ,  Michael Smith ,  David Wang ,  Frederick Weber

IPC分类号： G06F12/02 ,  G06F9/455

CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

公开(公告)号：US20080028136A1

公开(公告)日：2008-01-31

申请号：US11828181

申请日：2007-07-25

申请人： Keith Schakel ,  Suresh Rajan ,  Michael John Smith ,  David Wang

发明人： Keith Schakel ,  Suresh Rajan ,  Michael John Smith ,  David Wang

IPC分类号： G06F13/28

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  Y02D10/14

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

公开(公告)号：US07406041B2

公开(公告)日：2008-07-29

申请号：US10209545

申请日：2002-07-31

申请人： Rodney N. Mullendore ,  Stuart F. Oberman ,  Anil Mehta ,  Keith Schakel ,  Kamran Malik

发明人： Rodney N. Mullendore ,  Stuart F. Oberman ,  Anil Mehta ,  Keith Schakel ,  Kamran Malik

IPC分类号： H04L12/26

CPC分类号： H04L47/30 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/31 ,  H04L47/32 ,  H04L49/50

摘要： A system and method for late-dropping packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the switch may be subject to input thresholding, and may be assigned to a flow within a group. A portion of a packet subject to input thresholding may be accepted into the switch and assigned to a group and flow even if, at the time of arrival of the portion, there are not enough resources available to receive the remainder of the packet. This partial receipt of the packet is allowed because of the possibility of additional resources becoming available between the time of receipt of and resource allocation for the portion of the packet and receipt of subsequent portions of the packet.

摘要翻译： 一种用于在网络交换机中后期丢包的系统和方法。 网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。 进入交换机的数据包可能需要输入阈值，并且可以分配给组内的流。 即使在部分到达时，没有足够的资源可用于接收分组的其余部分，经过输入阈值处理的分组的一部分也可被接收到交换机中并分配给组和流。 允许分组的这种部分接收是因为在分组的接收时间和分组的部分和分组的后续部分的接收之间有额外的资源可用。

公开(公告)号：US20080109597A1

公开(公告)日：2008-05-08

申请号：US11929631

申请日：2007-10-30

申请人： Keith Schakel ,  Suresh Rajan ,  Michael Smith ,  David Wang

发明人： Keith Schakel ,  Suresh Rajan ,  Michael Smith ,  David Wang

IPC分类号： G06F13/38

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时 基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出

公开(公告)号：US20080109595A1

公开(公告)日：2008-05-08

申请号：US11929261

申请日：2007-10-30

申请人： Suresh Rajan ,  Keith Schakel ,  Michael Sebastian Smith ,  David Wang ,  Frederick Weber

发明人： Suresh Rajan ,  Keith Schakel ,  Michael Sebastian Smith ,  David Wang ,  Frederick Weber

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/28 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4093 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

摘要翻译： 提供了一种存储器电路系统和方法。 接口电路能够与多个存储器电路和系统通信。 在使用中，接口电路可操作以连接存储器电路和系统，以减少存储器电路的命令调度约束。

公开(公告)号：US20080080548A1

公开(公告)日：2008-04-03

申请号：US11871105

申请日：2007-10-11

申请人： Rodney Mullendore ,  Stuart Oberman ,  Anil Mehta ,  Keith Schakel ,  Kamran Malik

发明人： Rodney Mullendore ,  Stuart Oberman ,  Anil Mehta ,  Keith Schakel ,  Kamran Malik

IPC分类号： H04B7/212

CPC分类号： H04L49/103 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/357 ,  H04Q11/04 ,  H04Q2213/13292 ,  H04Q2213/13296 ,  H04Q2213/13332 ,  H04Q2213/13389

摘要： A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e.g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.

摘要翻译： 一种用于管理网络交换机中时分多路复用（TDM）时隙分配的系统和方法。 网络交换机可以使用包括多个时隙的TDM周期来管理共享资源，并且通过当前配置的端口来调度数据入口和出口，其中每个端口被分配一个或多个时隙。 网络交换机可以被重新编程以支持多个端口配置之一的多个时隙分配方案之一。 网络交换机可以支持具有不同数量端口的配置，例如， 8和16端口配置。 网络交换机还可以支持将两个或多个端口组合以形成一个端口（例如，2Gbs光纤通道端口）的配置。 为了满足各种配置的要求，时隙分配方案可以被重新编程以满足每个可能的端口配置的调度要求。

公开(公告)号：US20080037353A1

公开(公告)日：2008-02-14

申请号：US11584179

申请日：2006-10-20

申请人： Suresh Rajan ,  Keith Schakel ,  Michael Sebastian Smith ,  David Wang ,  Frederick Weber

发明人： Suresh Rajan ,  Keith Schakel ,  Michael Sebastian Smith ,  David Wang ,  Frederick Weber

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/04 ,  G11C5/145 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227 ,  G11C2207/2272

摘要： A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.

摘要翻译： 提供了存储器电路电源管理系统和方法。 在使用中，接口电路与多个存储器电路和系统通信。 接口电路可操作以将存储器电路和系统接口以与至少一部分存储器电路相关联地执行电力管理操作。 在与指向存储器电路的至少一部分的一个或多个命令相关联的延迟期间执行这种电力管理操作。

公开(公告)号：US20080109598A1

公开(公告)日：2008-05-08

申请号：US11929655

申请日：2007-10-30

申请人： Keith Schakel ,  Suresh Natarajan Rajan ,  Michael John Smith ,  David Wang

发明人： Keith Schakel ,  Suresh Natarajan Rajan ,  Michael John Smith ,  David Wang

IPC分类号： G06F13/00

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  Y02D10/14

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, dock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller. and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，该刷新命令序列包括适于从存储器控制器接收刷新命令的系统接口;停靠频率检测电路，被配置为确定向两个或多个耦合的存储器件发送交错刷新命令的定时 基于从存储器控制器接收的刷新命令到接口电路。 以及至少两个刷新命令序列输出，被配置为生成用于所述两个或更多个存储器设备的交错刷新命令