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    Serial data transferring apparatus
    3.
    发明申请
    Serial data transferring apparatus 有权
    串行数据传输设备

    公开(公告)号：US20050091428A1

    公开(公告)日：2005-04-28

    申请号：US10491285

    申请日：2001-10-02

    Applicant: Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Keiji Hanzawa ,  Hiroyasu Sukesako

    Inventor： Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Keiji Hanzawa ,  Hiroyasu Sukesako

    IPC: H04L7/02 ,  H04L7/04 ,  H04L7/06 ,  H04L7/10 ,  G06F3/00

    CPC classification number: H04L7/10 ,  H04J3/24 ,  H04J7/00 ,  H04L7/046 ,  H04L7/06

    Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.

    Abstract translation: 主单元向从单元发送启动信号。 当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号） 。 主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。 响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。 因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。 实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。

    Lighting apparatus, lighting control system and home electric appliance
    4.
    发明授权
    Lighting apparatus, lighting control system and home electric appliance 有权
    照明设备，照明控制系统和家用电器

    公开(公告)号：US06713975B2

    公开(公告)日：2004-03-30

    申请号：US09915365

    申请日：2001-07-27

    Applicant: Tatsumi Yamauchi ,  Fumio Murabayashi ,  Haruki Komatsu ,  Akio Inada

    Inventor： Tatsumi Yamauchi ,  Fumio Murabayashi ,  Haruki Komatsu ,  Akio Inada

    IPC: G05F100

    CPC classification number: H05B37/0254 ,  H05B37/0245 ,  Y02B20/40

    Abstract: A lighting apparatus capable of improving amenity and energy-saving and controlling a lighting load as a user intends to do. The lighting apparatus is connected to a network and controlling the lighting load corresponding to information from the network, and the lighting apparatus further comprises an automatic mode for controlling the lighting load corresponding to the information from the network, a manual mode for controlling the lighting load independently of the information from the network, and a switching means for switching between the automatic mode and the manual mode.

    Abstract translation: 一种照明装置，其能够改善舒适性和节能性并且控制用户打算做的照明负载。 照明装置连接到网络并控制与来自网络的信息相对应的照明负载，并且照明装置还包括用于控制与来自网络的信息相对应的照明负载的自动模式，用于控制照明负载的手动模式 独立于来自网络的信息，以及用于在自动模式和手动模式之间切换的切换装置。

    Waveform shaping device
    5.
    发明授权
    Waveform shaping device 失效
    波形整形装置

    公开(公告)号：US06437621B2

    公开(公告)日：2002-08-20

    申请号：US09816100

    申请日：2001-03-26

    Applicant: Kazuo Kato ,  Takashi Sase ,  Takashi Hotta ,  Fumio Murabayashi

    Inventor： Kazuo Kato ,  Takashi Sase ,  Takashi Hotta ,  Fumio Murabayashi

    IPC: H03K317

    CPC classification number: C08K5/5419 ,  C08G77/442 ,  C08G77/50 ,  C08L27/12 ,  C08L69/00

    Abstract: A waveform shaping circuit is provided so that the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency. An inverter which receives the clock pulses through an alternating current coupling capacitor is provided with a non-linear limiter element for limiting an amplitude of an output symmetrically on positive and negative sides thereof. A first current-limiting impedance and a second current-limiting impedance are connected between a power supply side terminal of the inverter and a power supply bus and between a grounding side terminal of the inverter and a grounding bus, respectively.

    Abstract translation: 提供波形整形电路，使得即使时钟脉冲是低电压和高频率，时钟脉冲的占空因数也可以高精度地设置为50％。 通过交流耦合电容器接收时钟脉冲的逆变器设置有非线性限制器元件，用于在其正侧和负侧对称地限制输出的幅度。 逆变器的电源侧端子与电源总线之间以及逆变器的接地侧端子与接地母线之间分别连接有第一限流阻抗和第二限流阻抗。

    Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them
    6.
    发明授权
    Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them 失效
    信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障

    公开(公告)号：US6101627A

    公开(公告)日：2000-08-08

    申请号：US206153

    申请日：1998-12-07

    Applicant: Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

    Inventor： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

    IPC: G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/30 ,  G06F13/00 ,  G06F15/78 ,  H02H3/05 ,  G06F7/02 ,  G06F11/08

    CPC classification number: G06F11/1637 ,  G06F11/1654 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

    Abstract: An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

    Abstract translation: 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。

    Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
    8.
    发明授权
    Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
    门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统

    公开(公告)号：US5677641A

    公开(公告)日：1997-10-14

    申请号：US423378

    申请日：1995-04-18

    Applicant: Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

    Inventor： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

    IPC: G11C11/41 ,  H03K3/3565 ,  H03K19/0185 ,  H03K19/0948

    CPC classification number: H03K3/3565 ,  H03K19/018521

    Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

    Abstract translation: 本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低幅度以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流 尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。 当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极 通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

    Current-driven signal interface implemented in semiconductor integrated circuit device
    9.
    发明授权
    Current-driven signal interface implemented in semiconductor integrated circuit device 失效
    电流驱动信号接口在半导体集成电路器件中实现

    公开(公告)号：US5363332A

    公开(公告)日：1994-11-08

    申请号：US860442

    申请日：1992-03-30

    Applicant: Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

    Inventor： Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

    IPC: H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  G11C8/00 ,  H01L27/06

    CPC classification number: H03K19/013 ,  H03K19/017518 ,  H03K19/01806

    Abstract: A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor. The arrangement results in reducing a signal amplitude on the signal bus, thereby speeding up the transmission of the data signal and reducing noise of the signal.

    Abstract translation: 半导体集成电路器件被布置为具有多个逻辑电路块，用于互连逻辑电路块的数据信号路径，并且用于提供与电流驱动信号接口的功能。 信号输出侧的逻辑电路块包括连接到数据信号路径的输出电路和由NMOS晶体管形成的开关元件，用于响应于施加到数据信号路径的输入端子的输入信号来控制流过数据信号路径的电流 输出电路。 信号输入侧的逻辑电路块包括连接到数据信号路径的输入电路。 输入电路包括具有连接到恒流源的发射极，形成输出端的集电极和固定电位的基极的双极晶体管。 从输出电路引出的数据信号路径连接到双极晶体管的发射极。 该结构可以减少信号总线上的信号幅度，从而加速数据信号的传输并降低信号的噪声。

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