Multi-port memory device
    2.
    发明申请
    Multi-port memory device 有权
    多端口存储设备

    公开(公告)号:US20050273670A1

    公开(公告)日:2005-12-08

    申请号:US10877837

    申请日:2004-06-25

    申请人: Byung-II Park

    发明人: Byung-II Park

    摘要: There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present. Therefore, the redundancy efficiency can be improved and an increase of the chip area can be prevented.

    摘要翻译: 提供了半导体存储器件的柱修复技术。 半导体存储器件包括:用于在全局数据总线与每个存储体的本地数据总线之间发送/接收数据的正常总线连接部分; 冗余总线连接部件,用于在全局数据总线与每个存储体的本地数据总线之间发送/接收数据; 具有故障列的物理位置信息的熔丝组; 以及切换部件,用于响应于故障列的物理位置信息,选择性地将正常总线连接部分和冗余总线连接部分的输出连接到对应于故障列的全局数据总线。 列冗余方案可以应用于具有这样一种结构的半导体存储器件,使得很多列选择线相对于一列地址被使能,并且还可以应用于不存在故障列地址的情况。 因此,可以提高冗余效率,并且可以防止芯片面积的增加。

    Multi-port memory device
    3.
    发明申请
    Multi-port memory device 有权
    多端口存储设备

    公开(公告)号:US20090059696A1

    公开(公告)日:2009-03-05

    申请号:US12288878

    申请日:2008-10-24

    申请人: Byung-II Park

    发明人: Byung-II Park

    摘要: There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present. Therefore, the redundancy efficiency can be improved and an increase of the chip area can be prevented.

    摘要翻译: 提供了半导体存储器件的柱修复技术。 半导体存储器件包括:用于在全局数据总线与每个存储体的本地数据总线之间发送/接收数据的正常总线连接部分; 冗余总线连接部件,用于在全局数据总线与每个存储体的本地数据总线之间发送/接收数据; 具有故障列的物理位置信息的熔丝组; 以及切换部件,用于响应于故障列的物理位置信息,选择性地将正常总线连接部分和冗余总线连接部分的输出连接到对应于故障列的全局数据总线。 列冗余方案可以应用于具有这样一种结构的半导体存储器件,使得很多列选择线相对于一列地址被使能,并且还可以应用于不存在故障列地址的情况。 因此,可以提高冗余效率,并且可以防止芯片面积的增加。