- 专利标题: Method for manufacturing a semiconductor device having a super junction MOSFET
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申请号: US15627434申请日: 2017-06-19
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公开(公告)号: US09954078B2公开(公告)日: 2018-04-24
- 发明人: Takahiro Tamura , Yasuhiko Onishi
- 申请人: FUJI ELECTRIC CO., LTD.
- 申请人地址: JP Kawasaki-Shi, Kanagawa
- 专利权人: FUJI ELECTRIC CO., LTD.
- 当前专利权人: FUJI ELECTRIC CO., LTD.
- 当前专利权人地址: JP Kawasaki-Shi, Kanagawa
- 代理机构: Rabin & Berdo, P.C.
- 优先权: JP2013-192789 20130918
- 主分类号: H01L21/265
- IPC分类号: H01L21/265 ; H01L29/66 ; H01L29/06
摘要:
A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n− region with a lower impurity concentration than the n-type drift region.
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