- 专利标题: Integrated circuit with self-verification function, verification method and method for generating a BIST signature adjustment code
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申请号: US14753032申请日: 2015-06-29
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公开(公告)号: US09885754B2公开(公告)日: 2018-02-06
- 发明人: Chi-Shun Weng , Chun-Yi Kuo
- 申请人: Realtek Semiconductor Corp.
- 申请人地址: TW HsinChu
- 专利权人: Realtek Semiconductor Corp.
- 当前专利权人: Realtek Semiconductor Corp.
- 当前专利权人地址: TW HsinChu
- 代理商 Winston Hsu
- 优先权: TW103123374A 20140707
- 主分类号: G01R29/00
- IPC分类号: G01R29/00 ; G01R31/3193 ; G01R31/3187
摘要:
An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error.
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