- Patent Title: Electronic component package and method for manufacturing the same
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Application No.: US14422972Application Date: 2013-12-20
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Publication No.: US09825209B2Publication Date: 2017-11-21
- Inventor: Kazuma Mima , Seiichi Nakatani , Yoshihisa Yamashita , Koji Kawakita , Susumu Sawada
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2012-279972 20121221
- International Application: PCT/JP2013/007505 WO 20131220
- International Announcement: WO2014/097645 WO 20140626
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/00 ; H01L33/00 ; H01L23/02 ; H01L23/52 ; H01L29/40 ; C25D7/12 ; C25D11/32 ; H01L33/62 ; H01L33/64 ; H01L21/48 ; H01L33/52 ; H01L21/768 ; H01L21/56

Abstract:
A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.
Public/Granted literature
- US20150221842A1 ELECTRONIC COMPONENT PACKAGE AND METHOD FOR PRODUCING SAME Public/Granted day:2015-08-06
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