- 专利标题: Digital clamp for state retention
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申请号: US15331280申请日: 2016-10-21
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公开(公告)号: US09722606B2公开(公告)日: 2017-08-01
- 发明人: Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G05F1/10
- IPC分类号: G05F1/10 ; G05F1/59 ; H03K19/00 ; G05F1/46 ; G06F1/32 ; H03K3/037
摘要:
Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.
公开/授权文献
- US20170041001A1 DIGITAL CLAMP FOR STATE RETENTION 公开/授权日:2017-02-09
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