Invention Grant
- Patent Title: Threshold based multi-level cell programming for reliability improvement
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Application No.: US14702770Application Date: 2015-05-04
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Publication No.: US09679652B2Publication Date: 2017-06-13
- Inventor: Hiroshi Watanabe
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: Jianq Chyun IP Office
- Main IPC: G11C16/14
- IPC: G11C16/14 ; G11C16/10 ; G11C16/04 ; G11C11/56

Abstract:
A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.
Public/Granted literature
- US20160329103A1 MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT Public/Granted day:2016-11-10
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