Invention Grant
- Patent Title: Synchronous bus architecture for digital pre-distortion system
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Application No.: US14580158Application Date: 2014-12-22
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Publication No.: US09665510B2Publication Date: 2017-05-30
- Inventor: Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
- Applicant: Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agent Charles E. Bergere
- Main IPC: G06F13/24
- IPC: G06F13/24 ; G06F13/28 ; H03F1/32 ; H04B1/04

Abstract:
A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.
Public/Granted literature
- US20160179715A1 SYNCHRONOUS BUS ARCHITECTURE FOR DIGITAL PRE-DISTORTION SYSTEM Public/Granted day:2016-06-23
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