Invention Grant
- Patent Title: High power transistor with oxide gate barriers
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Application No.: US14531575Application Date: 2014-11-03
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Publication No.: US09640620B2Publication Date: 2017-05-02
- Inventor: Nicholas Stephen Dellas
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Tuenlap D. Chan; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L29/40 ; H01L21/28 ; H01L23/29 ; H01L29/51 ; H01L29/778 ; H01L29/10
Abstract:
A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.
Public/Granted literature
- US20160126330A1 THERMAL TREATED SEMICONDUCTOR/GATE DIELECTRIC INTERFACE FOR GROUP IIIA-N DEVICES Public/Granted day:2016-05-05
Information query
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