A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.