发明授权
- 专利标题： Input-output buffer circuit with a gate bias generator
- 专利标题（中）： 具有栅极偏置发生器的输入输出缓冲电路
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申请号： US14058117申请日： 2013-10-18
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公开(公告)号： US09385718B1公开(公告)日： 2016-07-05
- 发明人: Jun Liu , Yanzhong Xu , Bonnie I. Wang , Jeffrey T. Watt
- 申请人： Altera Corporation
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 主分类号： H03K19/00
- IPC分类号： H03K19/00 ; H03K19/0175 ; H03K19/017
摘要：
An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.
公开/授权文献
- US1233614A Soldering-iron. 公开/授权日：1917-07-17
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