Described is a pulse width modulation architecture for high speed digitally controlled voltage regulator. Described is an apparatus which comprises: a first phase interpolator (PI) for coupling an input to a delay element of a delay line, wherein the coupling is via a selection unit; a second PI for coupling an output of the delay element of the delay line, wherein the coupling is via the selection unit; and a third PI for providing an output, the third PI calibrated according to delay settings of the first and second PIs.