发明授权
- 专利标题： Manufacturing method of wafer level chip scale package structure
- 专利标题（中）： 晶圆级芯片尺寸封装结构的制造方法
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申请号： US14694256申请日： 2015-04-23
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公开(公告)号： US09337049B1公开(公告)日： 2016-05-10
- 发明人: Chih Cheng Hsieh , Hsiu Wen Hsu
- 申请人： NIKO SEMICONDUCTOR CO., LTD. , SUPER GROUP SEMICONDUCTOR CO., LTD.
- 申请人地址： TW New Taipei TW New Taipei
- 专利权人： NIKO SEMICONDUCTOR CO., LTD.,SUPER GROUP SEMICONDUCTOR CO., LTD.
- 当前专利权人： NIKO SEMICONDUCTOR CO., LTD.,SUPER GROUP SEMICONDUCTOR CO., LTD.
- 当前专利权人地址： TW New Taipei TW New Taipei
- 代理机构： Li & Cai Intellectual Property (USA) Office
- 优先权： TW103136129A 20141020
- 主分类号： H01L21/56
- IPC分类号： H01L21/56 ; H01L21/304 ; H01L21/306 ; H01L21/78 ; H01L29/78 ; H01L21/768 ; H01L21/48
摘要：
A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.
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