发明授权
US09331039B2 Semiconductor device including a buffer layer structure for reducing stress
有权
包括用于减轻应力的缓冲层结构的半导体器件
- 专利标题： Semiconductor device including a buffer layer structure for reducing stress
- 专利标题（中）： 包括用于减轻应力的缓冲层结构的半导体器件
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申请号： US14746183申请日： 2015-06-22
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公开(公告)号： US09331039B2公开(公告)日： 2016-05-03
- 发明人: Takeshi Yuzawa , Masatoshi Tagaki
- 申请人： SEIKO EPSON CORPORATION
- 申请人地址： JP Tokyo
- 专利权人： SEIKO EPSON CORPORATION
- 当前专利权人： SEIKO EPSON CORPORATION
- 当前专利权人地址： JP Tokyo
- 代理机构： Oliff PLC
- 优先权： JP2006-128360 20060502
- 主分类号： H01L29/40
- IPC分类号： H01L29/40 ; H01L21/44 ; H01L23/00 ; H01L23/522 ; H01L23/498 ; H01L23/48 ; H01L23/528 ; H01L23/532
摘要：
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
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