发明授权
US09294103B2 Pre-program of clock generation circuit for faster lock coming out of reset
有权
时钟发生电路的预编程,用于更快地锁定复位
- 专利标题: Pre-program of clock generation circuit for faster lock coming out of reset
- 专利标题(中): 时钟发生电路的预编程,用于更快地锁定复位
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申请号: US14180976申请日: 2014-02-14
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公开(公告)号: US09294103B2公开(公告)日: 2016-03-22
- 发明人: Jong-Suk Lee , Shih-Chieh R. Wen , Toshinari Takayanagi , Wei-Han Lien
- 申请人: Apple Inc.
- 申请人地址: US CA Cupertino
- 专利权人: Apple Inc.
- 当前专利权人: Apple Inc.
- 当前专利权人地址: US CA Cupertino
- 代理机构: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- 代理商 Erik A. Heter
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; H03L7/08 ; H03K5/00
摘要:
A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.
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