Invention Grant
US09261940B2 Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times
有权
存储器系统通过监视峰值信号来控制多个存储器的峰值电流产生，以使每个存储器的内部时钟以不同时间的处理器时钟同步
- Patent Title: Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times
- Patent Title (中): 存储器系统通过监视峰值信号来控制多个存储器的峰值电流产生，以使每个存储器的内部时钟以不同时间的处理器时钟同步
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Application No.: US13396618Application Date: 2012-02-15
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Publication No.: US09261940B2Publication Date: 2016-02-16
- Inventor: Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
- Applicant: Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2011-0017293 20110225; KR10-2011-0063039 20110628
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F13/42 ; H04L5/00 ; H04L7/00 ; G06F1/32 ; G06F1/14 ; G06F13/16 ; G06F1/04 ; G11C7/22
Abstract:
A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
Public/Granted literature
- US20120221880A1 MEMORY SYSTEM AND METHOD OF CONTROLLING SAME Public/Granted day:2012-08-30
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