Invention Grant
US09224863B2 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer
有权
通过在种子层的基础上提供嵌入式应变诱导半导体材料来提高晶体管的性能
- Patent Title: Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer
- Patent Title (中): 通过在种子层的基础上提供嵌入式应变诱导半导体材料来提高晶体管的性能
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Application No.: US13483481Application Date: 2012-05-30
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Publication No.: US09224863B2Publication Date: 2015-12-29
- Inventor: Peter Javorka , Stephan Kronholz , Gunda Beernink
- Applicant: Peter Javorka , Stephan Kronholz , Gunda Beernink
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Priority: DE102011076696 20110530
- Main IPC: H01L27/095
- IPC: H01L27/095 ; H01L29/78 ; H01L29/10 ; H01L29/165 ; H01L29/417 ; H01L29/66 ; H01L21/8234 ; H01L29/51

Abstract:
In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.
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