发明授权
- 专利标题： Error correction processing circuit and error correction processing method
- 专利标题（中）： 纠错处理电路和纠错处理方法
-
申请号： US13488741申请日： 2012-06-05
-
公开(公告)号： US09166739B2公开(公告)日： 2015-10-20
- 发明人: Toshiharu Sakai , Ryoji Azumi , Kiyomasa Nishisaka , Daisuke Hirata , Hiroyuki Kitajima
- 申请人： Toshiharu Sakai , Ryoji Azumi , Kiyomasa Nishisaka , Daisuke Hirata , Hiroyuki Kitajima
- 申请人地址： JP Kawasaki
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 当前专利权人地址： JP Kawasaki
- 代理机构： Staas & Halsey LLP
- 优先权： JP2011-140977 20110624
- 主分类号： H04Q11/04
- IPC分类号： H04Q11/04 ; G06F11/07 ; H04L15/00 ; H04L1/00 ; H03M13/15 ; H03M13/00
摘要：
An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.
公开/授权文献
信息查询
