发明授权
US09032343B1 Integrating multiple FPGA designs by merging configuration settings
有权
通过合并配置设置集成多个FPGA设计
- 专利标题： Integrating multiple FPGA designs by merging configuration settings
- 专利标题（中）： 通过合并配置设置集成多个FPGA设计
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申请号： US14106088申请日： 2013-12-13
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公开(公告)号： US09032343B1公开(公告)日： 2015-05-12
- 发明人: David Samuel Goldman
- 申请人： Altera Corporation
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Weaver Austin Villeneuve & Sampson LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.
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