A memory may comprise a first bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, a second bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, and a control circuit configured to activate, in the case where a word line corresponding to an inputted address among the first to Nth word lines in a bank selected between the first bank and the second bank is replaced with a Kth (1≦K≦M) redundancy word line among the first to Mth redundancy word lines during an operation in a first mode, at least one adjacent word line adjacent to the Kth redundancy word line of the selected bank.