发明授权
US09029988B2 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance 有权
通过n +外延晶片中的硅通孔减少寄生电容

Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
摘要:
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
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