发明授权
US09029988B2 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
有权
通过n +外延晶片中的硅通孔减少寄生电容
- 专利标题: Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
- 专利标题(中): 通过n +外延晶片中的硅通孔减少寄生电容
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申请号: US13743882申请日: 2013-01-17
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公开(公告)号: US09029988B2公开(公告)日: 2015-05-12
- 发明人: Kangguo Cheng , Subramanian S. Iyer , Pranita Kerber , Ali Khakifirooz
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Cantor Colburn LLP
- 代理商 Steven Meyers
- 主分类号: H01L29/40
- IPC分类号: H01L29/40 ; H01L23/04 ; H01L29/80 ; H01L23/538 ; H01L23/48
摘要:
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
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