发明授权
- 专利标题： Integrating optimal planar and three-dimensional semiconductor design layouts
- 专利标题（中）： 整合最优平面和三维半导体设计布局
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申请号： US13792946申请日： 2013-03-11
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公开(公告)号： US08966423B2公开(公告)日： 2015-02-24
- 发明人: Navneet Jain , Yunfei Deng , Mahbub Rashed , David Doman , Qi Xiang , Jongwook Kye
- 申请人： GLOBALFOUNDARIES Inc.
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Ditthavong & Steiner, P.C.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.
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