The array substrate 20 of the present invention includes pixel electrodes 25 formed in an area demarcated by a plurality of gate wiring lines 26 and source wiring lines 27 that intersect each other, and capacitance wiring lines 126 that are arranged in parallel with the gate wiring lines 26 and that form a capacitance with the pixel electrodes 25. The capacitance wiring lines 126 are arranged overlapping outer edges of the adjacent pixel electrodes 25, and formed on the capacitance wiring line 126 are: a first insulating film that covers the capacitance wiring line 126; a second insulating film 29 that is an insulating film formed on the first insulating film, and that has a protruding band part 129 with a line width narrower than the capacitance wiring line 126 and arranged along the capacitance wiring line 126. The pixel electrodes 25 are above the second insulating film 29 and are formed so the outer edges 125 of the adjacent pixel electrodes 25 and 25 ride up on the protruding band part 129.