Invention Grant
- Patent Title: Wafer grounding design for single pad lapping
- Patent Title (中): 单垫研磨的晶圆接地设计
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Application No.: US13690685Application Date: 2012-11-30
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Publication No.: US08956200B2Publication Date: 2015-02-17
- Inventor: David P. Druist , Glenn P. Gee , Unal M. Guruz , Edward H. Lee , David J. Seagle , Darrick T. Smith
- Applicant: HGST Netherlands B.V.
- Applicant Address: NL Amsterdam
- Assignee: HGST Netherlands B.V.
- Current Assignee: HGST Netherlands B.V.
- Current Assignee Address: NL Amsterdam
- Agency: Patterson & Sheridan, LLP
- Main IPC: B24B37/005
- IPC: B24B37/005 ; B24B49/10 ; G11B5/48

Abstract:
Embodiments described herein generally relate to connecting Electronic Lapping Guides (ELG) to a lapping controller to reduce resistance from current crowding while reducing connections to the ELG. A device and a system can include a wafer with peripheral grounding vias having a radius of at least 10 μm, a plurality of sliders with a magnetoresistive (MR) elements; a plurality of ELG electrically coupled to the lapping controller through a combination of the wafer and grounding pads and a bonding pad electrically coupled to the ELG. The ELG or the bonding pad can be positioned in the kerf or the device region of a row. If the ELG and the bonding pad are positioned in separate regions, a noble metal should be used to connect. Further, the number of grounding pads can be reduced by using grounding vias at specific intervals and specific sizes.
Public/Granted literature
- US20140154952A1 WAFER GROUNDING DESIGN FOR SINGLE PAD LAPPING Public/Granted day:2014-06-05
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