Invention Grant
US08878337B1 Integrated circuit structure having a capacitor structured to reduce dishing of metal layers
有权
具有电容器的集成电路结构，其构造为减少金属层的凹陷
- Patent Title: Integrated circuit structure having a capacitor structured to reduce dishing of metal layers
- Patent Title (中): 具有电容器的集成电路结构，其构造为减少金属层的凹陷
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Application No.: US13186279Application Date: 2011-07-19
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Publication No.: US08878337B1Publication Date: 2014-11-04
- Inventor: Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
- Applicant: Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent Raymond R. Moser, Jr.; LeRoy D. Maunu; Lois D. Cartier
- Main IPC: H01L21/02
- IPC: H01L21/02
Abstract:
A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
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