Invention Grant
US08735273B2 Forming wafer-level chip scale package structures with reduced number of seed layers
有权
形成具有减少种子层数的晶片级芯片级封装结构
- Patent Title: Forming wafer-level chip scale package structures with reduced number of seed layers
- Patent Title (中): 形成具有减少种子层数的晶片级芯片级封装结构
-
Application No.: US13179299Application Date: 2011-07-08
-
Publication No.: US08735273B2Publication Date: 2014-05-27
- Inventor: Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
- Applicant: Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.
Public/Granted literature
- US20130009307A1 Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers Public/Granted day:2013-01-10
Information query
IPC分类:
