发明授权
- 专利标题: Twin MONOS array for high speed application
- 专利标题(中): 双MONOS阵列用于高速应用
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申请号: US12079966申请日: 2008-03-31
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公开(公告)号: US08633544B2公开(公告)日: 2014-01-21
- 发明人: Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
- 申请人: Kimihiro Satoh , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Yoshitaka Baba
- 申请人地址: US OR Hillsboro
- 专利权人: Halo LSI, Inc.
- 当前专利权人: Halo LSI, Inc.
- 当前专利权人地址: US OR Hillsboro
- 代理机构: Saile Ackerman LLC
- 代理商 Stephen B. Ackerman; Rosemary L. S. Pike
- 主分类号: H01L29/772
- IPC分类号: H01L29/772
摘要:
A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
公开/授权文献
- US20080186763A1 Twin MONOS array for high speed application 公开/授权日:2008-08-07
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