Invention Grant
- Patent Title: Passivation layer for packaged chip
- Patent Title (中): 封装芯片的钝化层
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Application No.: US13313747Application Date: 2011-12-07
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Publication No.: US08558229B2Publication Date: 2013-10-15
- Inventor: Shin-Puu Jeng , Wei-Cheng Wu , Shang-Yun Hou , Chen-Hua Yu , Tzuan-Horng Liu , Tzu-Wei Chiu , Kuo-Ching Hsu
- Applicant: Shin-Puu Jeng , Wei-Cheng Wu , Shang-Yun Hou , Chen-Hua Yu , Tzuan-Horng Liu , Tzu-Wei Chiu , Kuo-Ching Hsu
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
Public/Granted literature
- US20130147032A1 PASSIVATION LAYER FOR PACKAGED CHIP Public/Granted day:2013-06-13
Information query
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