发明授权
- 专利标题: Rendering processing apparatus, parallel processing apparatus, and exclusive control method
- 专利标题(中): 渲染处理装置,并行处理装置和排他控制方法
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申请号: US11793640申请日: 2006-07-25
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公开(公告)号: US08363059B2公开(公告)日: 2013-01-29
- 发明人: Junichi Naoi
- 申请人: Junichi Naoi
- 申请人地址: JP
- 专利权人: Sony Computer Entertainment Inc.
- 当前专利权人: Sony Computer Entertainment Inc.
- 当前专利权人地址: JP
- 代理机构: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- 优先权: JP2005-315753 20051031
- 国际申请: PCT/JP2006/314616 WO 20060725
- 国际公布: WO2007/052394 WO 20070510
- 主分类号: G06F15/00
- IPC分类号: G06F15/00 ; G06F15/16 ; G06F15/80 ; G06F9/30 ; G06F9/40 ; G06T1/00
摘要:
A DDA 34 notifies the coordinates of a rasterized pixel to an exclusive control part 40, acquires a unique identification number associated with the pixel position from the exclusive control part 40, and adds the identification number to pixel data and supplies it to a shader 20. A plurality of shader pipes 22 in the shader 20 perform arithmetic processing for rendering pixels in parallel, and writes the processing results to a frame buffer 50. When performing an arithmetic instruction that requires exclusive control over a pixel, each shader pipe 22 issues a request to lock the pixel by notifying the identification information added to that pixel to the exclusive control part 40. If the lock request is accepted, the shader pipe 22 performs the arithmetic processing on that pixel. If the lock request is rejected, the shader pipe suspends and puts the arithmetic processing on that pixel into a wait state, and executes arithmetic processing on another pixel in the interim.
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