Invention Grant
- Patent Title: Chip package structure and manufacturing method thereof for effectively lowering manufacturing costs and improving yield and reliability of the chip package structure
- Patent Title (中): 芯片封装结构及其制造方法，用于有效降低制造成本并提高芯片封装结构的产量和可靠性
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Application No.: US12542154Application Date: 2009-08-17
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Publication No.: US08242594B2Publication Date: 2012-08-14
- Inventor: Chung-Pan Wu
- Applicant: Chung-Pan Wu
- Applicant Address: TW Taoyuan
- Assignee: Unimicron Technology Corp.
- Current Assignee: Unimicron Technology Corp.
- Current Assignee Address: TW Taoyuan
- Agency: J.C. Patents
- Priority: TW98112809A 20090417
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/48 ; H01L21/44
Abstract:
A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.
Public/Granted literature
- US20100264534A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2010-10-21
Information query
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