A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and a second pattern, and the first pattern has a first critical dimension (CD) distribution, and the second pattern has a second CD distribution. The reference bit lines have the first pattern and the second pattern. The reference bit line selection circuit provides a reference signal by selecting a reference bit line having a same pattern as a selected memory bit line connected to a memory cell to be read.