发明授权
- 专利标题: Uniformity for semiconductor patterning operations
- 专利标题(中): 半导体图案化操作的均匀性
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申请号: US12014958申请日: 2008-01-16
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公开(公告)号: US07926001B2公开(公告)日: 2011-04-12
- 发明人: Christophe Pierrat
- 申请人: Christophe Pierrat
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Sheppard Mullin Richter & Hampton LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G03F1/00 ; H01L21/302
摘要:
Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a layer of a semiconductor device, wherein the original patterns of sacrificial material are used to define placement of spacer material to define patterning of circuit elements for the semiconductor device; determining densities of the plurality of original patterns of sacrificial material in areas across a portion of the layer of the semiconductor device; and augmenting the dataset to include an additional pattern of sacrificial material in an area of the layer having a density lower than a threshold density.
公开/授权文献
- US20100299646A1 UNIFORMITY FOR SEMICONDUCTOR PATTERNING OPERATIONS 公开/授权日:2010-11-25
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