Invention Grant
- Patent Title: Method of manufacturing a multilayered printed circuit board
- Patent Title (中): 制造多层印刷电路板的方法
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Application No.: US12098582Application Date: 2008-04-07
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Publication No.: US07832098B2Publication Date: 2010-11-16
- Inventor: Naohiro Hirose , Kouta Noda , Hiroshi Segawa , Honjin En , Kiyotaka Tsukada , Naoto Ishida , Kouji Asano , Atsushi Shouda
- Applicant: Naohiro Hirose , Kouta Noda , Hiroshi Segawa , Honjin En , Kiyotaka Tsukada , Naoto Ishida , Kouji Asano , Atsushi Shouda
- Applicant Address: JP Ogaki-shi
- Assignee: IBIDEN Co., Ltd.
- Current Assignee: IBIDEN Co., Ltd.
- Current Assignee Address: JP Ogaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP10-249382 19980903; JP10-281940 19980916; JP10-281942 19980916; JP10-303247 19981009; JP11-043514 19990222; JP11-043515 19990222; JP11-060240 19990308; JP11-116246 19990423
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
Public/Granted literature
- US20080189943A1 MULTILAYERED PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF Public/Granted day:2008-08-14
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