Invention Grant
- Patent Title: Shallow trench isolation process and structure with minimized strained silicon consumption
- Patent Title (中): 浅沟槽隔离工艺和结构,使应变硅消耗最小化
-
Application No.: US12115473Application Date: 2008-05-05
-
Publication No.: US07732336B2Publication Date: 2010-06-08
- Inventor: Qi Xiang , James N. Pan , Jung-Suk Goo
- Applicant: Qi Xiang , James N. Pan , Jung-Suk Goo
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong, Mori & Steiner, P.C.
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
Public/Granted literature
- US20080213952A1 SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION Public/Granted day:2008-09-04
Information query
IPC分类: