Invention Grant
- Patent Title: Flip chip and wire bond semiconductor package
- Patent Title (中): 倒装芯片和引线键合半导体封装
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Application No.: US11718396Application Date: 2005-10-31
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Publication No.: US07554185B2Publication Date: 2009-06-30
- Inventor: Chee Seng Foong , Aminuddin Ismail , Wai Yew Lo , Bee Hoon Liau , Jin- Mei Liu , Jian- Hong Wang , Jin- Zhong Yao , Fu- Bin Song
- Applicant: Chee Seng Foong , Aminuddin Ismail , Wai Yew Lo , Bee Hoon Liau , Jin- Mei Liu , Jian- Hong Wang , Jin- Zhong Yao , Fu- Bin Song
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Priority: MYPI20045136 20041214
- International Application: PCT/US2005/039610 WO 20051031
- International Announcement: WO2006/065378 WO 20060622
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A semiconductor package and method of forming the package, including a substrate having an opening formed therein. Contact pads are formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate. A flip chip die is mounted to the substrate, having an active side mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.
Public/Granted literature
- US20080111248A1 Flip Chip And Wire Bond Semiconductor Package Public/Granted day:2008-05-15
Information query
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